Many conventional electronic devices utilize a testing scheme for circuit components coupled to a memory. Because the contents of the memory may be unknown during the testing process and therefore may result in spurious test results, test data typically is input to the data path at the output of the memory via a test data source. Thus, conventional testing schemes typically are implemented by using a multiplexer to select between the latched output of the memory and the test data. However, the data path from the output of the memory typically is a critical path during normal operation and introduction of the additional logic gates of the multiplexer directly into this critical path typically introduces an undesirable delay in this critical path. Accordingly, an improved technique for bypassing a latch would be advantageous.
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